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//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor             : Xilinx
// \   \   \/     Version            : 1.1
//  \   \         Application        : MIG
//  /   /         Filename           : ddr4_v2_2_17_cal_wr_byte.sv
// /___/   /\     Date Last Modified : $Date: 2015/04/23 $
// \   \  /  \    Date Created       : Thu Apr 18 2013
//  \___\/\___\
//
// Device           : UltraScale
// Design Name      : DDR4 SDRAM & DDR3 SDRAM
// Purpose          :
//                   ddr4_v2_2_17_cal_wr_byte module
// Reference        :
// Revision History :
//*****************************************************************************

`timescale 1ns/100ps

module ddr4_v2_2_17_cal_wr_byte #
  (
   parameter TCQ = 0.1
   )
   (
    input clk
   ,input rst

   ,output  [7:0] mcal_DMOut_n
   ,output [63:0] mcal_DQOut

   ,input [63:0] DQOut
   ,input  [7:0] DMOut
   ,input        wrDataVal
   ,input  [2:1] wrOffset
);

genvar bNum;
generate
   for (bNum = 0; bNum <= 7; bNum++) begin:genBit
      ddr4_v2_2_17_cal_wr_bit #
        (
         .TCQ   (TCQ)
         )
        u_ddr_mc_wr_bit (
          .clk (clk)
         ,.rst (rst)

         ,.mcal_DOut (mcal_DQOut[bNum*8+:8])

         ,.DQOut     (DQOut[bNum*8+:8])
         ,.wrDataVal (wrDataVal)
         ,.wrOffset  (wrOffset)
      );
   end
endgenerate

ddr4_v2_2_17_cal_wr_bit #
  (
   .TCQ   (TCQ)
   )
 
  u_ddr_mc_wr_dm (
    .clk (clk)
   ,.rst (rst)

   ,.mcal_DOut (mcal_DMOut_n)

   ,.DQOut     (DMOut)
   ,.wrDataVal (wrDataVal)
   ,.wrOffset  (wrOffset)
);

endmodule


